xilinx - Connecting ports by name in VHDL, UCF-style -
i have vhdl entity defined this:
entity realentity port( clk_50mhz: in std_logic; led : out std_logic_vector(3 downto 0) ); end realentity;
if have ucf entries led<0>..led<3>
, clk_50mhz
, can compile entity directly.
however, don't have 50 mhz clock on board, have use clock manager chip. i'm using xilinx tools has wizard add dcm core, , wrap in vhdl entity easy use:
entity dcm port( clk_32mhz: in std_logic; clk_50mhz: out std_logic ); end dcm;
where clk_32mhz
exists in ucf.
to connect these two, using third entity used toplevel one:
entity main port( clk_32mhz : in std_logic; led : out std_logic_vector(3 downto 0) ); end main; architecture arch of main signal clk_50mhz : std_logic; component dcm port( clk_32mhz : in std_logic; clk_50mhz : out std_logic ); end component; component realentity port(clk_50mhz : in std_logic; led : out std_logic_vector(3 downto 0) ); end component; begin inst_dcm : dcm port map( clk_32mhz => clk_32mhz, clk_50mhz => clk_50mhz ); inst_realentity : realentity port map( clk_50mhz => clk_50mhz, led => led ); end arch;
as can see, third entity 100% boilerplate. question is, possible avoid writing main
entity, , instead use realentity
, dcm
directly, , connect 2 clk_50mhz
ports virtue of them sharing name, emulating clk_50mhz
being present in ucf file?
somehow have tell tools how wire dcm , real entity. "boilerplate" top-level entity achieves that. can't in ucf file doesn't allow create connections, attach various attributes connections have made.
so problem becomes 1 of tools exist enable "wire things up" efficiently possible. brian has enumerated options there...
you can reduce boilerplate using direct instantiation. remove component
declarations , do:
inst_realentity : entity work.realentity port map( clk_50mhz => clk_50mhz, led => led );
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